System and method for providing stable control for power systems

ABSTRACT

System and method for providing stable control for power systems. According to an embodiment, the present invention provides an apparatus for providing one or more control signals for a power system. The apparatus includes an input terminal for receiving an electrical energy, which can be characterized by a first input voltage. The apparatus includes a control component that is configured to generate a first control signal based on at least information associated with the first input voltage. The apparatus additionally includes an output terminal for sending the first control signal. Moreover, the apparatus includes a timing component that is coupled to the control component. The control component is configured to process at least information associated with a first value of the first input voltage at a first time and a first reference voltage and to generate a second control signal.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No.200710038167.7, filed Mar. 13, 2007, entitled “SYSTEM AND METHOD FORPROVIDING STABLE CONTROL FOR POWER SYSTEMS”, by inventors Yuan Lin, JunYe, and Lieyi Fang, commonly assigned, incorporated by reference hereinfor all purposes.

BACKGROUND OF THE INVENTION

The present invention is related to integrated circuits. Morespecifically, the present invention can be applied to devices usedcontrolling power supply. According to various embodiments, the presentinvention provides various power control schemes to improve systemstability and performance. Merely by way of example, the presentinvention can be used in switch mode power conversion system includingpower-on reset and under voltage lockout circuits. It is to beappreciated that the present invention has a broad range ofapplications.

Power converters are widely used in various applications, such asproviding power to portable consumer electronics. The power converterscan convert electric power from one form to another form. As an example,the electric power is transformed from alternate current (AC) to directcurrent (DC), from DC to AC, from AC to AC, or from DC to DC.Additionally, the power converters can convert electric power from onevoltage level to another voltage level. By converting electrical powerto desired form and/or voltage, various devices can be properly powered.

In the past various types of power converters have been developed. Forexample, linear regulators have traditionally been used for powerconverters. A linear regulator is a voltage regulator based on an activedevice (such as a bipolar junction transistor, field effect transistoror vacuum tube) operating in its “linear region” or passive devices likezener diodes operated in their breakdown region. The regulating deviceis made to act like a variable resistor. While linear regulators havebeen used for many years, their power efficiency is often inadequate forportable electronics. For example, due to low power efficiency, linearregulators often waste large amount of energy and generate excessiveheat for portable devices.

With the advent of integrated circuits, switched-mode power supply hasbeen invented and utilized for various applications. Switch mode powersupplies are typically implemented with a switching regulator, which isan internal control circuit that switches the load current rapidly onand off in order to stabilize the output voltage. For certainapplications, switch-mode power supply uses pulse-width-modulated (PWM)or pulse-frequency-modulated (PFM) mechanism. These mechanisms areusually implemented with a switch-mode-controller including variousprotection components.

Typically, various types of power supplies are controlled by power-onreset (POR) and under voltage lockout (UVLO) circuits. For example,POR/UVLO circuits are used to hold the electronic systems in a “reset”mode during power on and off transitions. In addition, POR and UVLOcircuits are sometimes used when the power supply voltage, whichtypically ranges from several volts to several tens of volts, is in aninvalid state.

When an integrated circuit initializes (e.g., when powering up), theprocess usually starts with the supply voltage of the integrated circuitbeing switched on. During this process, the supply voltage will risefrom zero to an operational supply voltage within a certain amountsource impedance or source current. Before the operational supplyvoltage is reached, the integrated circuit is unable to properlyfunction. Typically, the integrated circuit at this voltage is in anundefined and/or invalid state. For example, when the integrated circuitis at an undefined state, the integrated circuit should not operate;operating in an undefined state could potentially cause damages to theintegrated circuit.

As explained above, it is thus desirable to prevent the integratedcircuit from operating when it is in an undefined and/or invalid state(e.g., due to insufficient supply voltage). To disable integratedcircuit form operating in an undefined state, the integrated circuit isusually put in to a reset mode, which can be accomplished by an UVLOcircuit.

In addition to preventing the integrated circuit from operating when itis in an undefined and/or invalid state, it is often desirable to assurethat various components of the integrated circuit are in a properlyinitialized before the integrated circuit starts fully operating.Usually, a POR/UVLO circuit is used to monitor voltages at various nodesof the integrated circuits to determine whether various components areproperly initialized (e.g., whether these components reached theirthreshold voltage levels). Based on the monitored voltages, the POR/UVLOgenerates control signals that enable and/or disable various componentsand/or the integrated circuit.

Over the past, POR/UVLO circuits have widely used for various powersystems. Conventional techniques for POR/UVLO power control have beendeveloped to make POR/UVLO circuits more efficient and reliable.Unfortunately, these conventional techniques are often inadequate.

Therefore, it is desirable to have improved systems and methods forpower control systems.

BRIEF SUMMARY OF THE INVENTION

The present invention is related to integrated circuits. Morespecifically, the present invention can be applied to devices usedcontrolling power supply. According to various embodiments, the presentinvention provides various power control schemes to improve systemstability and performance. Merely by way of example, the presentinvention can be used in switch mode power conversion system includingpower-on reset and under voltage lockout circuits. It is to beappreciated that the present invention has a broad range ofapplications.

In certain embodiments, the present invention is implemented with poweron-reset (POR) and under voltage lock out (UVLO) circuit. For example,certain POR/UVLO circuits according to present invention are used asparts of switched power conversion controllers, which can be used toinitialize integrated pulse width modulation (PWM) circuits. In aspecific embodiment, a POR/UVLO circuit according to the presentinvention utilizes a timing device to prevent undesirable toggling ofcontrol signals, which often occurs when the a power system in operatingin light-to-heavy load transition.

According to an embodiment, the present invention provides an apparatusfor providing one or more control signals for a power system. Theapparatus includes an input terminal for receiving an electrical energy,which can be characterized by a first input voltage. The apparatus alsoincludes a control component that is configured to generate a firstcontrol signal based on at least information associated with the firstinput voltage. The apparatus additionally includes an output terminalfor sending the first control signal. Moreover, the apparatus includes atiming component that is coupled to the control component. The controlcomponent is further configured to process at least informationassociated with a first value of the first input voltage at a first timeand a first reference voltage and to generate a second control signalbased on at least information associated with the first voltage and thefirst reference voltage. The timing component is configured to receivethe second control signal and in response to the second control signalto generate a third control signal after a period of time delay. Thecontrol component is further configured to receive the third controlsignal and, in response to the third control signal, process informationassociated with a second value of the first input voltage at a secondtime and the first reference voltage and to generate the first controlsignal based on at least information associated with the first voltageand the first reference voltage. The first control signal is capable tocause one or more components of the power system to be turned off.

According to another embodiment, the present invention provides anapparatus for providing one or more control signals for a power system.The apparatus includes an input terminal for receiving electricalenergy, which is characterized by a first voltage. The apparatus alsoincludes a control component that is configured to generate a controlsignal based on the first voltage. The control signal is capable tocause one or more components of the power system to be turned on or off.The control component is further configured to compare the first voltageto a first reference voltage and a second reference voltage. The firstreference voltage is lower than the second reference voltage. Theapparatus additionally includes an output terminal for sending thecontrol signal. Moreover the apparatus includes a timer that isconfigured to provided a delay time. The control component generates anon signal if the first voltage rises above the second reference voltage.The timer initiates if the first voltage drops below the first referencevoltage at a first time. The control component generates an off signalif the first voltage is below the first reference voltage at a secondtime. For example, the second time is elapse of delay time after thefirst time.

According to yet another embodiment, the present invention provides amethod for providing one or more control signals for a power system. Themethod includes a step for providing a first reference voltage and asecond reference voltage. The first reference voltage is lower than thesecond reference voltage. The method also includes a step fordetermining a voltage that is associated with a load condition of thepower system. The method further includes a step for providing a firstsignal if the voltage rises above the second reference voltage. Thefirst signal is capable of causing one or more components of the powersystem to be turned on. The method also includes a step for initiating atimer if the voltage drops below the first reference voltage at a firsttime. Moreover, the method includes a step for providing a second signalif the voltage is below the first reference voltage at a second time.The second time is later than the first time by a predetermined amountof time. For example, the second signal is capable of causing the one ormore components of the power system to be turn off.

According to yet another embodiment, the present invention provides amethod for providing one or more control signals for a power system. Themethod includes a step for receiving an electrical energy that ischaracterized by a first input voltage. The method also includes a stepfor providing a first reference voltage and a second reference voltage.The method additionally includes a step for processing at leastinformation associated with a first value of the first input voltage ata first time and a first reference voltage by a control component. As anexample, the control component is configured to generate a first controlsignal. The method additionally includes a step for generating a secondcontrol signal based on at least information associated with the firstvoltage and the first reference voltage. Moreover, the method includes astep for sending the second control signal to a timing component.Furthermore, the method includes a step for sending a third controlsignal to the control component by the timing component after a periodof time delay. Additionally, the method includes a step for processinginformation associated with a second value of the first input voltage ata second time and the first reference voltage by the control component.Also, the method includes a step for generating the first control signalbased on at least information associated with the first voltage and thefirst reference voltage. The first control signal is capable to causeone or more components of the power system to be turned off.

It is to be appreciated that the present invention provides variousadvantages over conventional techniques. According to an embodiment, thepresent invention provides a more energy efficient solution as comparedto conventional techniques. For example, the present invention reducesthe numbers of transitions between on and off states of a power supply.More specifically, embodiments of the present invention reduces thenumber of undesirable transition between on and off due to glitches inthe power system. According to certain embodiment, the present inventionoffers a large window for power control and great flexibility. Forexample, more than one threshold voltage threshold values are used indetermining various states of the power supply. In addition, it is to beappreciated that various embodiments of the present invention arecompatible and easily implemented with conventional systems. There areother benefits as well.

Various additional objects, features and advantages of the presentinvention can be more fully appreciated with reference to the detaileddescription and the accompanying drawings that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram illustrating a conventional power system.

FIG. 2 is a simplified diagram illustrating a conventional POR/UVLOcircuit as used in a power system.

FIG. 3 is a simplified timing diagram illustrating the operation of aPOR/UVLO circuit.

FIG. 4 is a simplified timing diagram illustrating operation ofconventional POR/UVLO circuits.

FIG. 5 is a simplified diagram illustrating a POR/UVLO circuit accordingto an embodiment of the present invention

FIG. 6 is a simplified flow diagram illustrating operation of a powercontrol component according to an embodiment of the present invention.

FIG. 7 is a simplified diagram illustrating a control system accordingto an embodiment of the present invention.

FIG. 8 is a simplified timing diagram illustrating the operation of acontrol system according to an embodiment of the present invention

DETAILED DESCRIPTION OF THE INVENTION

The present invention is related to integrated circuits. Morespecifically, the present invention can be applied to devices usedcontrolling power supply. According to various embodiments, the presentinvention provides various power control schemes to improve systemstability and performance. Merely by way of example, the presentinvention can be used in switch mode power conversion system includingpower-on reset and under voltage lockout circuits. It is to beappreciated that the present invention has a broad range ofapplications.

As described above, power-on reset (POR) and under voltage lockout(UVLO) circuits are widely used for power systems. Typically,characteristics of operation of POR/UVLO circuits are related to variousparameters (e.g., impedance level, power input, etc.).

FIG. 1 is a simplified diagram illustrating a conventional power system.A conventional power system 100 includes an AC power supply 102, whichis rectified by the rectifier 103, and the supplied to a PWM controllercircuit 110 through a resistor 101 (i.e., often referred to as startupresistor). The resistor 101 is a necessary for starting a PWM signalgenerator 112. At the same time, the resistor 101 is often a source ofsignificant energy inefficient during the operation of the PWM signalgenerator 112, as the resistor 101 is typically characterized by largeimpedance value (up to several mega ohms). For example, between the twoterminals of the resistor 101, difference in voltage potential betweennode 106 and node 107 is great. As an example, the voltage at node 106can be at 370 volts DC while the VDD voltage at the node 107 is as lowas 12 volts DC. Thus, the large voltage drop due to the resistor 101during the continuous operation of the power system leads to significantenergy loss, especially when the power system 100 is operating in lightor no load conditions. In addition to energy inefficiency, the largevalue of the resistor 101 also leads to low source current (e.g., as lowas several tens of micro amps) supplied to the PWM generator 112. It istherefore desirable to have a POR/UVLO circuit with low quiescentcurrent consumption.

FIG. 2 is a simplified diagram illustrating a conventional POR/UVLOcircuit as used in a power system. A POR/UVLO circuit 200 turns on oroff based its input voltage and reference voltages UVLO(OFF) andUVLO(ON). For example, a hysteresis voltage between UVLO(OFF) andUVLO(ON) prevents the supply voltage VDD (e.g., voltage at node 107 inFIG. 1) from being unstable during power on/off sequences. As anexample, during a startup process, the power system is turned on whenthe capacitor 120 (as shown in FIG. 1) is charged up to UVLO(OFF)voltage level through the resistor 101 (as shown in FIG. 1).

During, the output 201 of the POR/UVLO circuit 200 is controlled by theswitches 202 and 203. For example, when the VDD voltage ramps up toUVLO(OFF) at node 204, both switches are turned on, and as a result thePOR output 205 changes from zero to one. As an example, when the VDDvoltage drops (e.g., during a process of powering off), the switches 202and 203 are turned off, which causes the POR output 204 to change from“1” to “0”.

In certain applications, the output 201 of the POR/UVLO circuit 200 canbe used to control a high-to-low voltage regulator (e.g., a part of theinterval low voltage components). For example, when the voltage at node204 drops below threshold voltage UVLO(ON), the POR output 204 is low,which disables the high-to-low regulator.

The POR output 204 depends on the VDD voltage, the UVLO(ON) voltage, andthe UVLO(OFF) voltage. Based on the diagram as shown in FIG. 2, theUVLO(ON) voltage may be expressed by the following equation.

UVLO(ON)=V _(th) _(—) _(M1) +V _(DZ2) +V _(D1)  (Equation 1)

In Equation 1, the V_(th) _(—) _(M1) voltage represents the voltage ofthe switch 202, the V_(DZ2) represents the voltage of the diode 213, andthe term V_(D1) represents the voltage of the diode 212.

Similarly, the UVLO(OFF) voltage may be expressed by the followingequation.

UVLO(OFF)=V _(th) _(—) _(M1) +V _(DZ2) +V _(D1) +V _(DZ1)  (Equation 2)

In Equation 2, the V_(th) _(—) _(M1) voltage represents the voltage ofthe switch 202, the V_(DZ2) represents the voltage of the diode 213, theterm V_(D1) represents the voltage of the diode 212, and the termV_(DZ1) represents the voltage of the diode 211.

FIG. 3 is a simplified timing diagram illustrating the operation of aPOR/UVLO circuit. As shown in FIG. 3, the POR output changes from zeroto one when the VDDH voltage rises above the UVLO(OFF) voltage; the PORvoltage changes from one to zero when the VDDH voltages drops below theUVLO(ON) voltage.

A conventional POR/UVLO circuit as shown in FIG. 2 is effective inpreventing a power system from damages under various conditions.Unfortunately, such conventional POR/UVLO circuit is often inefficientand unstable. For example, a temporary supply voltage fluctuation of thepower system could lead the POR/UVLO circuit to send a reset signal tothe power system, causing the power system to shut down and restart. Asan example, sudden temporary drop in supply voltage occurs when thepower system experiences a transition of system load from light toheavy.

Typically, when load of the power system is light, the supply voltage(i.e., VDD voltage) is close to UVLO(ON). When load on the power systemincreases abruptly, the supply voltage usually drops temporarily.Typically, the voltage drop of the supply voltage is due to finite loopbandwidth and transformer coupling (e.g., see couple 140 in FIG. 1)between a secondary side and auxiliary side, which provides energy toPWM controller (e.g., PWM controller 110 in FIG. 1). Usually, theheavier is the loading transition, the larger is the supply voltagedrop. In certain occasions, when the loading transition is heavy enough,the supply voltage would drop below the UVLO(ON) voltage, causing systemto restart.

FIG. 4 is a simplified timing diagram illustrating operation ofconventional POR/UVLO circuits. As seen in FIG. 4, abrupt loadingchanges could result in undesired UVLO process. For example, the loadingis suddenly increased at t₁. The VDD voltage level, due to the suddenincrease of the load, drops drastically at t₁. At t₂, the VDD voltagelevel drops below the threshold voltage level UVLO(ON), causing thePOR/UVLO circuit to stop PWM switching at t₂. The drop in VDD voltagelevel, however, is only temporary. As shown, the power supply steadilyramps up the VDD voltage at t₂ in response to the loading increase. Att₃, the VDD voltage is increased to a voltage level that is higher thanthe threshold voltage level UVLO(OFF), causing the POR/UVLO circuit torestart PWM switching.

While the POR/UVLO circuits are designed to protect a power system frombeing damaged from sudden change in operational parameters in a powercircuit, shutting down the PWM switching for the abovementioned scenariois generally undesirable. For example, the drop of the VDD voltage isonly temporary, and thus shutting down the PWM switching is unnecessaryand undesirable. For example, between t₂ and t₃, the PWM switchingremains off despite the fact that the VDD voltage is not low enough towarrant turning off of PWM switching. In addition, undesired shuttingoff of PWM switching renders the power system less stable and subject torestarts caused by minor glitches.

It is to be appreciated that certain embodiments of the presentembodiments provide stable and efficient method and system forcontrolling power system. For example, a specific embodiment of thepresent invention involves a technique for improving system stability ofa power system by reducing and/or eliminating undesirable shutting offthe system.

In a specific embodiment, the present invention provides a POR/UVLOcircuit that includes a mechanism for reducing and/or eliminatingundesirable shutting off of the system. FIG. 5 is a simplified diagramillustrating a POR/UVLO circuit according to an embodiment of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims. One of ordinary skill in the artwould recognize many variations, alternatives, and modifications.

As shown in FIG. 5, a control system 500 includes, but not limited to,the following components:

1. a voltage input 501;

2. a voltage sensor 502;

3. a voltage regulator 503;

4. a voltage comparator 553;

5. a reference voltage 554;

6. a timer 552;

7. switches 512, 513, and 514; and

8. an AVDD component.

The control system 500 is capable of, like conventional POR/UVLOcircuits, causes various components of a power system to be turned on oroff based on one or more input voltages. As shown in FIG. 5, the controlsystem 500 includes a POR/UVLO circuit 510. The POR/UVLO circuit 510 isa part of the control system 500 and includes the voltage input 501,switches 512, 513, and 514, and a POR output 590. Now referring back tothe control system 500, which includes the timer 552 that is connectedto the comparator 553. For example, the timer 552 is a delay timer thatdelays the output of the comparator 553 before the output is supplied tothe POR/UVLO circuit 510 for the determination of whether a power offsignal is to be sent. Depending upon application, the timer 552 may beimplemented in various ways. Merely by way of example, the timer 552 maybe implemented by an RC filter, which timing characteristics are basedon the values of resistors and capacitors. Also, the timer 552 may beimplemented with other means, such as latches, oscillators, etc.

In a specific embodiment, the present invention implements the timer 552using a timer circuit. It is to be appreciated that the timer circuitoccupies less chip area and is able to generate time delayscharacterized by different properties as compared to an RC timer. Forexample, a timer circuit according to a specific embodiment of theinvention is implemented within a small chip area.

As shown in FIG. 5, the POR/UVLO circuit 510 can be characterized by alatch structure and two threshold voltages: UVLO(OFF) and UVLO(ON)threshold voltages. The POR/UVLO circuit 500 has a voltage input 501,which is electrically coupled to a power supply at a terminal VDDH 504.For example, the UVLO(OFF) voltage is associated with the voltage at theterminal VDDH 504. Depending upon application, the POR/UVLO circuit 501may receive other signal inputs. For example, a different input signalis used to control the UVLO(ON) voltage. The POR output 590 is suppliedto the voltage regulator 503, which in turn provides low voltage supplysignal to the AVDD component 550. In addition the low voltage supplysignal, the AVDD component 550 also receives a signal from the VDDHsensor 502. For example, the VDDH sensor 502 provides a scaled VDDHsignal based on specific applications.

The VDDH sensor 502 may be implemented in various ways. For example, theVDDH sensor is implemented by a resistor divider, which can be combinedwith the POR/UVLO circuit 510. The scaled VDDH signal from the VDDHsensor 502 is provided to the comparator 553 of the AVDD component. Inaddition to the scaled VDDH signal from the VDDH sensor 502, thecomparator also receives a reference voltage from the reference voltageinput 554. As an example, the reference voltage may be adjustedaccording to specific application.

The comparator 553 compares the reference voltage and the scaled VDDHsignal and generates a comparator output signal to the timer 552. Amongother things, the timer 552 is able to debounce the comparator outputsignal for a predetermined time. For example, if the scaled VDDH signalis lower than the reference voltage for the predetermined time, theoutput of the timer 552 causes the POR/UVLO circuit 510 to change state,thereby changes the POR output 590 from one to zero. On the other hand,if the scaled VDDH signal is lower than the reference voltage for lessthe predetermined time, the output of the timer 552 does not cause thePOR/UVLO circuit 510 to change state. It is to be appreciated that basedon specific applications, the predetermined time may be adjusted.Typically, the predetermined time is long enough to prevent undesiredshutting down of the system due to temporary system glitch yet is nottoo long to hinder the proper functioning of the power system.

It is to be appreciated that the control system 500 may be implementedto adaptable for implementation with conventional power systems. Forexample, the control system 500 is implemented in conjunction with thepower system 100 as illustrated in FIG. 1.

To further illustrate the operation of the present invention, a flowdiagram is presented. FIG. 6 is a simplified flow diagram illustratingoperation of a power control component according to an embodiment of thepresent invention. This diagram is merely an example, which could bealtered and modified, and should not unduly limit the scope of claims.For example, various steps as illustrated in FIG. 6 may be added,removed, replaced, rearranged, repeated, overlapped, and/or partiallyoverlapped. Merely by way of an example, a flow diagram 600 illustratesthe operation of the control system 500 that is used to provide controlfor a power system. For example, the power system is similar to thepower system 100 in various ways.

At step 601, the power system is set to a start up state. Typically,before the power system receives power input from one or more powersupply, various components should be turned off to prevent thesecomponents from being damaged. For example, the control system 500 sendsa signal indicating that POR=0, which consequently causes variouscomponents (e.g., PWM switching component, etc.) to be turned off.

At step 602, the power system is turned on. According to variousembodiments, the power system is turned on when a power supply that isconnected to the power system is turned on. To ensure the properfunctioning of power system and components thereof, the power systemdoes not turn on all its components before it is determined that thepower level at the power system is stable and operations. For example,before the power from power supply is provided to the PWM switchingcomponent of the power system, the control system 500 determines whetherthe power system and power system are in working order.

At step 603, the control system determines whether the supply voltagehas reached an operational threshold. According to an embodiment, thecontrol system compares the VDD supply voltage against a predeterminedthreshold voltage level UVLO(OFF). If the VDD supply voltage is greaterthan the UVLO(OFF) voltage, the control system proceeds to step 604. Asexplained above, the UVLO(OFF) voltage is a threshold voltage thatindicates whether the supply voltage is sufficient enough to allow thepower system to properly operate. Depending upon application, theUVLO(OFF) voltage may be modified based on the specific needs. On theother hand, if the VDD supply voltage is less than the UVLO(OFF)voltage, the control system repeats step 603 after a predetermined timeperiod.

At step 604, the control system generates a signal to turn on the powersystem. In a specific application, the control system provides a signalindicating POR=1, enabling PWM switching of the power system, thusturning on various components of the power system.

At step 605, the control system determines whether the supply voltagehas dropped below a threshold voltage. In an embodiment, the thresholdvoltage is UVLO(ON) voltage. Merely by way of an example, the controlsystem constantly monitors the supply voltage level in real time. If theVDD supply voltage is less than the UVLO(ON) voltage, the control systemproceeds to step 605. As explained above, the UVLO(ON) voltage is athreshold voltage that indicates whether the supply voltage is too lowto warrant the power system being turned off. Depending uponapplication, the UVLO(ON) voltage may be modified based on the specificneeds. On the other hand, if the VDD supply voltage is greater than theUVLO(ON) voltage, the control system proceeds to step 604 after apredetermined time period.

At step 606, the control system determines whether the supply voltage isbelow the UVLO(ON) threshold after an elapse of a predetermined time.For example, the timer 552 in FIG. 5 causes the control system to waitfor the predetermined time before the control system sends controlsignals for turning the power system off. In a specific embodiment,after the predetermined time, the control system compares the supplyvoltage with the UVLO(ON) voltage. If the VDD supply voltage is lessthan the UVLO(ON) voltage, the control system proceeds to step 601(i.e., turning off and resetting the power system). On the other hand,if the VDD supply voltage is greater than the UVLO(ON) voltage, thecontrol system proceeds to step 604.

FIG. 7 is a simplified diagram illustrating a control system accordingto an embodiment of the present invention. This diagram is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications.

As shown in FIG. 7, a control system 700 includes, among other things,the following components:

1. zener diodes 701 and 703;

2. a diode 702;

3. resistors 705, 706, 708, and 715;

4. switches 704, 707, and 709;

5. an inverter 710;

6. a voltage regulator 711;

7. a reference voltage 714;

8. a comparator 713; and

9. a timer 712.

As an example, the control system 700 operates in essentially the sameway as the control system 500. According to certain embodiments, thecontrol system 700 is compatible with conventional power systems (e.g.,the power system 100 in FIG. 1). It is to be appreciated that thecontrol system 700 may be flexibility implemented using various types ofcomponents. For example, switches 704, 707, and 709 is implemented usingMOSFETs in certain applications, but can be implemented using othertypes of devices as well (e.g., BJT, etc.). Similarly, the timer 712 maybe implemented with various types of devise as well, which is explainedabove. For example, the timer 712 is implemented using low-voltagedevice, as relatively long period of delay time may be achieved usingfrequency divided PWM clock.

The control system 700 generates control signals, which are producedfrom switches. The output of POR output 750 is triggered by the switch707. For example, the switch 707 is implemented with a high voltage NMOSin conjunction with resistor 708 and a voltage divider. Merely by way ofexample, the voltage divider is implemented using resistors 705 and 706connected in series, which is for sensing the VDDH voltage.

The voltage level determination is performed by the voltage comparator713. In some embodiments, the voltage comparator 713 is a low voltagecomparator. The Voltage comparator 713 is connected to the referencevoltage 714 to determine whether the supply voltage VDD is above one ormore threshold voltages. As an example, the output of the voltagecomparator 713 is delayed by the timer 712, which uses an internaloscillator clock of the PWM controller as one of its input.

The operation of the control system 700 may be illustrated thefollowings. When the power is turned on for the system, the controlsystem 700 provides the POR signal without delay by the timer 712. Forexample, when the power system turns on, before the POR signal switchesfrom zero to one, the voltage regulator is at a disabled state. As aresult, no power is available to various components of the controlsystem. For example, when no power is available various components(e.g., switch 707) may be in undefined states. The resistor 708 is usedto eliminate undefined states of these components, and thus the switch707 is not triggered when the voltage regulator 711 is not ready.

When the power system powers off, the supply voltage VDDH ramps down. Atcertain point, the supply voltage VDDH drops below a predeterminedvoltage UVLO(ON). When this happens, the timer 712 is triggered to delaythe comparator output for a predetermined time. When the predeterminedtime, the output of the comparator 713 is passed through the timer 712to the switch 707, which turns on or off switches 704 and 709. If thepredetermined time is not yet over, the output of the comparator 713cannot passed through the timer 712. During the operation, the resistor708 functions as a pull down resistor that is used to ensure properoperation of the switches after the power system is on.

According to certain implementation of the control system 700, twoUVLO(ON) voltages are used. For example, a UVLO(ON) voltage is inaccordance with functions of the timer 715 while a UVLO(ON)_H voltagefunctions in essentially the same way as a conventional UVLO(ON)threshold voltage. For example, the UVLO(ON) voltage is associated withthe timer 712. For the two UVLO(ON) voltage thresholds to properlyfunction in conjunction with the timer 712, the UVLO(ON) thresholdvoltage is higher than the UVLO(ON)_H threshold voltage, and the controlsystem 700 generates control signals based on the UVLO(ON) thresholdvoltage. As an example, the relationships among threshold voltages areillustrated according to the following equations.

$\begin{matrix}{{{UVLO}({ON})} = {{V_{th} \cdot \left( {1 + \frac{R_{1}}{R_{2}}} \right)} + V_{{DZ}\; 2} + V_{D\; 1}}} & \left( {{Equation}\mspace{14mu} 3} \right) \\{{{{UVLO}({ON})}{\_ H}} = {V_{{th\_ M}\; 2} + V_{{DZ}\; 2} + V_{D\; 1}}} & \left( {{Equation}\mspace{14mu} 4} \right) \\{{{UVLO}({ON})} \geq {{{UVLO}({ON})}{\_ H}}} & \left( {{Equation}\mspace{14mu} 5} \right)\end{matrix}$

FIG. 8 is a simplified timing diagram illustrating the operation of acontrol system according to an embodiment of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. As shown in FIG. 8, thecontrol system 700 changes the POR output from zero to one when VDDHramps up above the threshold voltage UVLO(OFF) at t1. When the VDDHvoltage drops below UVLO(ON) at t2, the control system changes the PORoutput from one to zero. As explained above, the UVLO(ON) voltagereferred here is different from the UVLO(ON) voltage used in aconventional power system. For example, the UVLO(ON) voltage accordingto the embodiments of the present invention is higher than the UVLO(ON)voltage of conventional power systems.

According to an embodiment, the present invention provides an apparatusfor providing one or more control signals for a power system. Theapparatus includes an input terminal for receiving an electrical energy,which can be characterized by a first input voltage. The apparatus alsoincludes a control component that is configured to generate a firstcontrol signal based on at least information associated with the firstinput voltage. The apparatus additionally includes an output terminalfor sending the first control signal. Moreover, the apparatus includes atiming component that is coupled to the control component. The controlcomponent is further configured to process at least informationassociated with a first value of the first input voltage at a first timeand a first reference voltage and to generate a second control signalbased on at least information associated with the first voltage and thefirst reference voltage. The timing component is configured to receivethe second control signal and in response to the second control signalto generate a third control signal after a period of time delay. Thecontrol component is further configured to receive the third controlsignal and, in response to the third control signal, process informationassociated with a second value of the first input voltage at a secondtime and the first reference voltage and to generate the first controlsignal based on at least information associated with the first voltageand the first reference voltage. The first control signal is capable tocause one or more components of the power system to be turned off. As anexample, the embodiment is illustrated according to FIG. 7.

According to another embodiment, the present invention provides anapparatus for providing one or more control signals for a power system.The apparatus includes an input terminal for receiving electricalenergy, which is characterized by a first voltage. The apparatus alsoincludes a control component that is configured to generate a controlsignal based on the first voltage. The control signal is capable tocause one or more components of the power system to be turned on or off.The control component is further configured to compare the first voltageto a first reference voltage and a second reference voltage. The firstreference voltage is lower than the second reference voltage. Theapparatus additionally includes an output terminal for sending thecontrol signal. Moreover the apparatus includes a timer that isconfigured to provided a delay time. The control component generates anon signal if the first voltage rises above the second reference voltage.The timer initiates if the first voltage drops below the first referencevoltage at a first time. The control component generates an off signalif the first voltage is below the first reference voltage at a secondtime. For example, the second time is elapse of delay time after thefirst time. As an example, the embodiment is illustrated according toFIG. 7.

According to yet another embodiment, the present invention provides amethod for providing one or more control signals for a power system. Themethod includes a step for providing a first reference voltage and asecond reference voltage. The first reference voltage is lower than thesecond reference voltage. The method also includes a step fordetermining a voltage that is associated with a load condition of thepower system. The method further includes a step for providing a firstsignal if the voltage rises above the second reference voltage. Thefirst signal is capable of causing one or more components of the powersystem to be turned on. The method also includes a step for initiating atimer if the voltage drops below the first reference voltage at a firsttime. Moreover, the method includes a step for providing a second signalif the voltage is below the first reference voltage at a second time.The second time is later than the first time by a predetermined amountof time. For example, the second signal is capable of causing the one ormore components of the power system to be turn off. As an example, theembodiment is illustrated according to FIG. 6.

According to yet another embodiment, the present invention provides amethod for providing one or more control signals for a power system. Themethod includes a step for receiving an electrical energy that ischaracterized by a first input voltage. The method also includes a stepfor providing a first reference voltage and a second reference voltage.The method additionally includes a step for processing at leastinformation associated with a first value of the first input voltage ata first time and a first reference voltage by a control component. As anexample, the control component is configured to generate a first controlsignal. The method additionally includes a step for generating a secondcontrol signal based on at least information associated with the firstvoltage and the first reference voltage. Moreover, the method includes astep for sending the second control signal to a timing component.Furthermore, the method includes a step for sending a third controlsignal to the control component by the timing component after a periodof time delay. Additionally, the method includes a step for processinginformation associated with a second value of the first input voltage ata second time and the first reference voltage by the control component.Also, the method includes a step for generating the first control signalbased on at least information associated with the first voltage and thefirst reference voltage. The first control signal is capable to causeone or more components of the power system to be turned off. As anexample, the embodiment is illustrated according to FIG. 6.

It is to be appreciated that the present invention provides variousadvantages over conventional techniques. According to an embodiment, thepresent invention provides a more energy efficient solution as comparedto conventional techniques. For example, the present invention reducesthe numbers of transitions between on and off states of a power supply.More specifically, embodiments of the present invention reduces thenumber of undesirable transition between on and off due to glitches inthe power system. According to certain embodiment, the present inventionoffers a large window for power control and great flexibility. Forexample, more than one threshold voltage threshold values are used indetermining various states of the power supply. In addition, it is to beappreciated that various embodiments of the present invention arecompatible and easily implemented with conventional systems. There areother benefits as well.

Although specific embodiments of the present invention have beendescribed, it will be understood by those of skill in the art that thereare other embodiments that are equivalent to the described embodiments.Accordingly, it is to be understood that the invention is not to belimited by the specific illustrated embodiments, but only by the scopeof the appended claims.

1.-26. (canceled)
 27. A controller for a power system, the controllercomprising: a first resistor including a first resistor terminal and asecond resistor terminal, the first resistor terminal configured toreceive a first voltage signal, the second resistor terminal beingconnected to a first circuit node; a first transistor including a firsttransistor terminal, a second transistor terminal, and a thirdtransistor terminal, the first transistor terminal being configured toreceive a second voltage signal from the first circuit node, the secondtransistor terminal being configured to receive a third voltage signalfrom a second circuit node, the third transistor terminal beingconnected to a third circuit node; a second resistor including a thirdresistor terminal and a fourth resistor terminal, the third resistorterminal being connected to the second circuit node; a third resistorincluding a fifth resistor terminal and a sixth resistor terminal, thefifth resistor terminal being connected to the fourth resistor terminalthrough a fourth circuit node, the sixth resistor terminal beingconnected to the third circuit node; a second transistor including afourth transistor terminal, a fifth transistor terminal, and a sixthtransistor terminal, the fourth transistor terminal being connected tothe second circuit node, the sixth transistor terminal being connectedto the third circuit node; a voltage regulator configured to receive atleast the first voltage signal and to convert the first voltage signalto a fourth voltage signal, the fourth voltage signal being smaller thanthe first voltage signal in magnitude; a threshold voltage generatorconfigured to receive the fourth voltage signal and to generate athreshold voltage signal; a voltage comparator configured to receive thethreshold voltage signal and a fifth voltage signal from the fourthcircuit node, compare the threshold voltage signal and the fifth voltagesignal, and to generate a comparison signal; and a timer configured toreceive the comparison signal, provide a delay time, and output a sixthvoltage signal.
 28. The controller of claim 27 is further configured: todetermine whether the fifth voltage signal is below the thresholdvoltage signal in magnitude at a first time; if the fifth voltage signalis determined to be below the threshold voltage signal in magnitude atthe first time, to determine again whether the fifth voltage signal isbelow the threshold voltage signal in magnitude at a second time, thesecond time being later than the first time by the delay time; and ifthe fifth voltage signal is determined to be below the threshold voltagesignal in magnitude at the first time and if the fifth voltage signal isalso determined to be below the threshold voltage signal in magnitude atthe second time, to provide an off signal as the power-on-reset signalto at least the voltage regulator.
 29. The controller of claim 28 isfurther configured, if the fifth voltage signal is determined to bebelow the threshold voltage signal in magnitude at the first time and ifthe fifth voltage signal is determined not to be below the thresholdvoltage signal in magnitude at the second time, not to provide the offsignal.
 30. The controller of claim 27, and further comprising a fourthresistor including a seventh resistor terminal and an eighth resistorterminal, the seventh resistor terminal being connected to the fifthtransistor terminal, the eighth resistor terminal being connected to thethird circuit node.
 31. The controller of claim 27 wherein the timerincludes an RC filter.
 32. The controller of claim 27 wherein the timerincludes a latch.
 33. The controller of claim 27, and further comprisingan oscillator configured to output a clock signal to the timer.
 34. Thecontroller of claim 27 wherein the delay time is predetermined.
 35. Thecontroller of claim 27, and further comprising: a first zener diodeincluding a first diode terminal and a second diode terminal, the firstdiode terminal configured to receive the first voltage signal; a thirdtransistor including a seventh transistor terminal, an eighth transistorterminal, and a ninth transistor terminal, the seventh transistorterminal configured to receive the first voltage signal, the eighthtransistor terminal being connected to the first circuit node, the ninthtransistor terminal being connected to the second diode terminal; afirst diode including a third diode terminal and a fourth diodeterminal, the third diode terminal being connected to the second diodeterminal; and a second zener diode including a fifth diode terminal anda sixth diode terminal, the fifth diode terminal being connected to thefourth diode terminal, the sixth diode terminal being connected to thesecond circuit node.
 36. The controller of claim 27 wherein the voltageregulator includes an inverter configured to receive the second voltagesignal at the first circuit node and to generate a power-on-reset signalbased on at least information associated with the second voltage signal.37. A method for providing one or more control signals for a powersystem, the method comprising: receiving a first voltage signal at afirst circuit node by an inverter; generating, by the inverter, apower-on-reset signal based on at least information associated with thefirst voltage signal; receiving a second voltage signal at a firstresistor terminal of a first resistor, the first resistor furtherincluding a second resistor terminal connected to the first circuitnode; receiving a third voltage signal from a second circuit node by afirst transistor terminal of a first transistor, the first transistorfurther including a second transistor terminal connected to the firstcircuit node and a third transistor terminal connected to a thirdcircuit node, the second circuit node being connected to a fourthtransistor terminal of a second transistor, the second transistorfurther including a fifth transistor terminal and a sixth transistorterminal connected to the third circuit node; receiving, by a voltageregulator, the second voltage signal and the power-on-reset signal;converting, by the voltage regulator, the second voltage signal to afourth voltage signal, the fourth voltage signal being smaller than thefirst voltage signal in magnitude; receiving, by a threshold voltagegenerator, the fourth voltage signal; generating, by the thresholdvoltage generator, a threshold voltage signal; receiving the thresholdvoltage signal and a fifth voltage signal from a fourth circuit node,the fourth circuit node being connected to a third resistor terminal ofa second resistor and a fourth resistor terminal of a third resistor,the second resistor further including a fifth resistor terminalconnected to the second circuit node, the third resistor furtherincluding a sixth resistor terminal connected to the third circuit node;determining whether the fifth voltage signal is below the thresholdvoltage signal in magnitude at a first time; if the fifth voltage signalis determined to be below the threshold voltage signal in magnitude atthe first time, determining again whether the fifth voltage signal isbelow the threshold voltage signal in magnitude at a second time, thesecond time being later than the first time by a delay time; and if andonly if the fifth voltage signal is determined to be below the thresholdvoltage signal in magnitude at the first time and if the fifth voltagesignal is also determined to be below the threshold voltage signal inmagnitude at the second time, providing an off signal as thepower-on-reset signal to at least the voltage regulator.
 38. The methodof claim 37 wherein the delay time is predetermined.
 39. The method ofclaim 37, and further comprising generating, by an oscillator, a clocksignal.
 40. The method of claim 37, and further comprising: receivingthe first voltage signal at a first diode terminal of a first zenerdiode, the first zener diode further including a second diode terminalconnected to a third diode terminal of a first diode, the first diodefurther including a fourth diode terminal, the fourth diode terminalbeing connected to a fifth diode terminal of a second zener diode, thesecond zener diode further including a sixth diode terminal connected tothe second circuit node; and receiving the first voltage signal at aseventh transistor terminal of a third transistor, the third transistorfurther including an eighth transistor terminal and a ninth transistorterminal, the eighth transistor terminal being connected to the firstcircuit node, the ninth transistor terminal being connected to thesecond diode terminal.